// Code generated by riscv64spec riscv-opcodes // DO NOT EDIT // Copyright 2024 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. package riscv64asm const ( _ Op = iota ADD ADDI ADDIW ADDW ADD_UW AMOADD_D AMOADD_D_AQ AMOADD_D_AQRL AMOADD_D_RL AMOADD_W AMOADD_W_AQ AMOADD_W_AQRL AMOADD_W_RL AMOAND_D AMOAND_D_AQ AMOAND_D_AQRL AMOAND_D_RL AMOAND_W AMOAND_W_AQ AMOAND_W_AQRL AMOAND_W_RL AMOMAXU_D AMOMAXU_D_AQ AMOMAXU_D_AQRL AMOMAXU_D_RL AMOMAXU_W AMOMAXU_W_AQ AMOMAXU_W_AQRL AMOMAXU_W_RL AMOMAX_D AMOMAX_D_AQ AMOMAX_D_AQRL AMOMAX_D_RL AMOMAX_W AMOMAX_W_AQ AMOMAX_W_AQRL AMOMAX_W_RL AMOMINU_D AMOMINU_D_AQ AMOMINU_D_AQRL AMOMINU_D_RL AMOMINU_W AMOMINU_W_AQ AMOMINU_W_AQRL AMOMINU_W_RL AMOMIN_D AMOMIN_D_AQ AMOMIN_D_AQRL AMOMIN_D_RL AMOMIN_W AMOMIN_W_AQ AMOMIN_W_AQRL AMOMIN_W_RL AMOOR_D AMOOR_D_AQ AMOOR_D_AQRL AMOOR_D_RL AMOOR_W AMOOR_W_AQ AMOOR_W_AQRL AMOOR_W_RL AMOSWAP_D AMOSWAP_D_AQ AMOSWAP_D_AQRL AMOSWAP_D_RL AMOSWAP_W AMOSWAP_W_AQ AMOSWAP_W_AQRL AMOSWAP_W_RL AMOXOR_D AMOXOR_D_AQ AMOXOR_D_AQRL AMOXOR_D_RL AMOXOR_W AMOXOR_W_AQ AMOXOR_W_AQRL AMOXOR_W_RL AND ANDI ANDN AUIPC BCLR BCLRI BEQ BEXT BEXTI BGE BGEU BINV BINVI BLT BLTU BNE BSET BSETI CLZ CLZW CPOP CPOPW CSRRC CSRRCI CSRRS CSRRSI CSRRW CSRRWI CTZ CTZW C_ADD C_ADDI C_ADDI16SP C_ADDI4SPN C_ADDIW C_ADDW C_AND C_ANDI C_BEQZ C_BNEZ C_EBREAK C_FLD C_FLDSP C_FSD C_FSDSP C_J C_JALR C_JR C_LD C_LDSP C_LI C_LUI C_LW C_LWSP C_MV C_NOP C_OR C_SD C_SDSP C_SLLI C_SRAI C_SRLI C_SUB C_SUBW C_SW C_SWSP C_UNIMP C_XOR DIV DIVU DIVUW DIVW EBREAK ECALL FADD_D FADD_H FADD_Q FADD_S FCLASS_D FCLASS_H FCLASS_Q FCLASS_S FCVT_D_L FCVT_D_LU FCVT_D_Q FCVT_D_S FCVT_D_W FCVT_D_WU FCVT_H_L FCVT_H_LU FCVT_H_S FCVT_H_W FCVT_H_WU FCVT_LU_D FCVT_LU_H FCVT_LU_Q FCVT_LU_S FCVT_L_D FCVT_L_H FCVT_L_Q FCVT_L_S FCVT_Q_D FCVT_Q_L FCVT_Q_LU FCVT_Q_S FCVT_Q_W FCVT_Q_WU FCVT_S_D FCVT_S_H FCVT_S_L FCVT_S_LU FCVT_S_Q FCVT_S_W FCVT_S_WU FCVT_WU_D FCVT_WU_H FCVT_WU_Q FCVT_WU_S FCVT_W_D FCVT_W_H FCVT_W_Q FCVT_W_S FDIV_D FDIV_H FDIV_Q FDIV_S FENCE FENCE_I FEQ_D FEQ_H FEQ_Q FEQ_S FLD FLE_D FLE_H FLE_Q FLE_S FLH FLQ FLT_D FLT_H FLT_Q FLT_S FLW FMADD_D FMADD_H FMADD_Q FMADD_S FMAX_D FMAX_H FMAX_Q FMAX_S FMIN_D FMIN_H FMIN_Q FMIN_S FMSUB_D FMSUB_H FMSUB_Q FMSUB_S FMUL_D FMUL_H FMUL_Q FMUL_S FMV_D_X FMV_H_X FMV_W_X FMV_X_D FMV_X_H FMV_X_W FNMADD_D FNMADD_H FNMADD_Q FNMADD_S FNMSUB_D FNMSUB_H FNMSUB_Q FNMSUB_S FSD FSGNJN_D FSGNJN_H FSGNJN_Q FSGNJN_S FSGNJX_D FSGNJX_H FSGNJX_Q FSGNJX_S FSGNJ_D FSGNJ_H FSGNJ_Q FSGNJ_S FSH FSQ FSQRT_D FSQRT_H FSQRT_Q FSQRT_S FSUB_D FSUB_H FSUB_Q FSUB_S FSW JAL JALR LB LBU LD LH LHU LR_D LR_D_AQ LR_D_AQRL LR_D_RL LR_W LR_W_AQ LR_W_AQRL LR_W_RL LUI LW LWU MAX MAXU MIN MINU MUL MULH MULHSU MULHU MULW OR ORC_B ORI ORN REM REMU REMUW REMW REV8 ROL ROLW ROR RORI RORIW RORW SB SC_D SC_D_AQ SC_D_AQRL SC_D_RL SC_W SC_W_AQ SC_W_AQRL SC_W_RL SD SEXT_B SEXT_H SH SH1ADD SH1ADD_UW SH2ADD SH2ADD_UW SH3ADD SH3ADD_UW SLL SLLI SLLIW SLLI_UW SLLW SLT SLTI SLTIU SLTU SRA SRAI SRAIW SRAW SRL SRLI SRLIW SRLW SUB SUBW SW XNOR XOR XORI ZEXT_H ) var opstr = [...]string{ ADD: "ADD", ADDI: "ADDI", ADDIW: "ADDIW", ADDW: "ADDW", ADD_UW: "ADD.UW", AMOADD_D: "AMOADD.D", AMOADD_D_AQ: "AMOADD.D.AQ", AMOADD_D_AQRL: "AMOADD.D.AQRL", AMOADD_D_RL: "AMOADD.D.RL", AMOADD_W: "AMOADD.W", AMOADD_W_AQ: "AMOADD.W.AQ", AMOADD_W_AQRL: "AMOADD.W.AQRL", AMOADD_W_RL: "AMOADD.W.RL", AMOAND_D: "AMOAND.D", AMOAND_D_AQ: "AMOAND.D.AQ", AMOAND_D_AQRL: "AMOAND.D.AQRL", AMOAND_D_RL: "AMOAND.D.RL", AMOAND_W: "AMOAND.W", AMOAND_W_AQ: "AMOAND.W.AQ", AMOAND_W_AQRL: "AMOAND.W.AQRL", AMOAND_W_RL: "AMOAND.W.RL", AMOMAXU_D: "AMOMAXU.D", AMOMAXU_D_AQ: "AMOMAXU.D.AQ", AMOMAXU_D_AQRL: "AMOMAXU.D.AQRL", AMOMAXU_D_RL: "AMOMAXU.D.RL", AMOMAXU_W: "AMOMAXU.W", AMOMAXU_W_AQ: "AMOMAXU.W.AQ", AMOMAXU_W_AQRL: "AMOMAXU.W.AQRL", AMOMAXU_W_RL: "AMOMAXU.W.RL", AMOMAX_D: "AMOMAX.D", AMOMAX_D_AQ: "AMOMAX.D.AQ", AMOMAX_D_AQRL: "AMOMAX.D.AQRL", AMOMAX_D_RL: "AMOMAX.D.RL", AMOMAX_W: "AMOMAX.W", AMOMAX_W_AQ: "AMOMAX.W.AQ", AMOMAX_W_AQRL: "AMOMAX.W.AQRL", AMOMAX_W_RL: "AMOMAX.W.RL", AMOMINU_D: "AMOMINU.D", AMOMINU_D_AQ: "AMOMINU.D.AQ", AMOMINU_D_AQRL: "AMOMINU.D.AQRL", AMOMINU_D_RL: "AMOMINU.D.RL", AMOMINU_W: "AMOMINU.W", AMOMINU_W_AQ: "AMOMINU.W.AQ", AMOMINU_W_AQRL: "AMOMINU.W.AQRL", AMOMINU_W_RL: "AMOMINU.W.RL", AMOMIN_D: "AMOMIN.D", AMOMIN_D_AQ: "AMOMIN.D.AQ", AMOMIN_D_AQRL: "AMOMIN.D.AQRL", AMOMIN_D_RL: "AMOMIN.D.RL", AMOMIN_W: "AMOMIN.W", AMOMIN_W_AQ: "AMOMIN.W.AQ", AMOMIN_W_AQRL: "AMOMIN.W.AQRL", AMOMIN_W_RL: "AMOMIN.W.RL", AMOOR_D: "AMOOR.D", AMOOR_D_AQ: "AMOOR.D.AQ", AMOOR_D_AQRL: "AMOOR.D.AQRL", AMOOR_D_RL: "AMOOR.D.RL", AMOOR_W: "AMOOR.W", AMOOR_W_AQ: "AMOOR.W.AQ", AMOOR_W_AQRL: "AMOOR.W.AQRL", AMOOR_W_RL: "AMOOR.W.RL", AMOSWAP_D: "AMOSWAP.D", AMOSWAP_D_AQ: "AMOSWAP.D.AQ", AMOSWAP_D_AQRL: "AMOSWAP.D.AQRL", AMOSWAP_D_RL: "AMOSWAP.D.RL", AMOSWAP_W: "AMOSWAP.W", AMOSWAP_W_AQ: "AMOSWAP.W.AQ", AMOSWAP_W_AQRL: "AMOSWAP.W.AQRL", AMOSWAP_W_RL: "AMOSWAP.W.RL", AMOXOR_D: "AMOXOR.D", AMOXOR_D_AQ: "AMOXOR.D.AQ", AMOXOR_D_AQRL: "AMOXOR.D.AQRL", AMOXOR_D_RL: "AMOXOR.D.RL", AMOXOR_W: "AMOXOR.W", AMOXOR_W_AQ: "AMOXOR.W.AQ", AMOXOR_W_AQRL: "AMOXOR.W.AQRL", AMOXOR_W_RL: "AMOXOR.W.RL", AND: "AND", ANDI: "ANDI", ANDN: "ANDN", AUIPC: "AUIPC", BCLR: "BCLR", BCLRI: "BCLRI", BEQ: "BEQ", BEXT: "BEXT", BEXTI: "BEXTI", BGE: "BGE", BGEU: "BGEU", BINV: "BINV", BINVI: "BINVI", BLT: "BLT", BLTU: "BLTU", BNE: "BNE", BSET: "BSET", BSETI: "BSETI", CLZ: "CLZ", CLZW: "CLZW", CPOP: "CPOP", CPOPW: "CPOPW", CSRRC: "CSRRC", CSRRCI: "CSRRCI", CSRRS: "CSRRS", CSRRSI: "CSRRSI", CSRRW: "CSRRW", CSRRWI: "CSRRWI", CTZ: "CTZ", CTZW: "CTZW", C_ADD: "C.ADD", C_ADDI: "C.ADDI", C_ADDI16SP: "C.ADDI16SP", C_ADDI4SPN: "C.ADDI4SPN", C_ADDIW: "C.ADDIW", C_ADDW: "C.ADDW", C_AND: "C.AND", C_ANDI: "C.ANDI", C_BEQZ: "C.BEQZ", C_BNEZ: "C.BNEZ", C_EBREAK: "C.EBREAK", C_FLD: "C.FLD", C_FLDSP: "C.FLDSP", C_FSD: "C.FSD", C_FSDSP: "C.FSDSP", C_J: "C.J", C_JALR: "C.JALR", C_JR: "C.JR", C_LD: "C.LD", C_LDSP: "C.LDSP", C_LI: "C.LI", C_LUI: "C.LUI", C_LW: "C.LW", C_LWSP: "C.LWSP", C_MV: "C.MV", C_NOP: "C.NOP", C_OR: "C.OR", C_SD: "C.SD", C_SDSP: "C.SDSP", C_SLLI: "C.SLLI", C_SRAI: "C.SRAI", C_SRLI: "C.SRLI", C_SUB: "C.SUB", C_SUBW: "C.SUBW", C_SW: "C.SW", C_SWSP: "C.SWSP", C_UNIMP: "C.UNIMP", C_XOR: "C.XOR", DIV: "DIV", DIVU: "DIVU", DIVUW: "DIVUW", DIVW: "DIVW", EBREAK: "EBREAK", ECALL: "ECALL", FADD_D: "FADD.D", FADD_H: "FADD.H", FADD_Q: "FADD.Q", FADD_S: "FADD.S", FCLASS_D: "FCLASS.D", FCLASS_H: "FCLASS.H", FCLASS_Q: "FCLASS.Q", FCLASS_S: "FCLASS.S", FCVT_D_L: "FCVT.D.L", FCVT_D_LU: "FCVT.D.LU", FCVT_D_Q: "FCVT.D.Q", FCVT_D_S: "FCVT.D.S", FCVT_D_W: "FCVT.D.W", FCVT_D_WU: "FCVT.D.WU", FCVT_H_L: "FCVT.H.L", FCVT_H_LU: "FCVT.H.LU", FCVT_H_S: "FCVT.H.S", FCVT_H_W: "FCVT.H.W", FCVT_H_WU: "FCVT.H.WU", FCVT_LU_D: "FCVT.LU.D", FCVT_LU_H: "FCVT.LU.H", FCVT_LU_Q: "FCVT.LU.Q", FCVT_LU_S: "FCVT.LU.S", FCVT_L_D: "FCVT.L.D", FCVT_L_H: "FCVT.L.H", FCVT_L_Q: "FCVT.L.Q", FCVT_L_S: "FCVT.L.S", FCVT_Q_D: "FCVT.Q.D", FCVT_Q_L: "FCVT.Q.L", FCVT_Q_LU: "FCVT.Q.LU", FCVT_Q_S: "FCVT.Q.S", FCVT_Q_W: "FCVT.Q.W", FCVT_Q_WU: "FCVT.Q.WU", FCVT_S_D: "FCVT.S.D", FCVT_S_H: "FCVT.S.H", FCVT_S_L: "FCVT.S.L", FCVT_S_LU: "FCVT.S.LU", FCVT_S_Q: "FCVT.S.Q", FCVT_S_W: "FCVT.S.W", FCVT_S_WU: "FCVT.S.WU", FCVT_WU_D: "FCVT.WU.D", FCVT_WU_H: "FCVT.WU.H", FCVT_WU_Q: "FCVT.WU.Q", FCVT_WU_S: "FCVT.WU.S", FCVT_W_D: "FCVT.W.D", FCVT_W_H: "FCVT.W.H", FCVT_W_Q: "FCVT.W.Q", FCVT_W_S: "FCVT.W.S", FDIV_D: "FDIV.D", FDIV_H: "FDIV.H", FDIV_Q: "FDIV.Q", FDIV_S: "FDIV.S", FENCE: "FENCE", FENCE_I: "FENCE.I", FEQ_D: "FEQ.D", FEQ_H: "FEQ.H", FEQ_Q: "FEQ.Q", FEQ_S: "FEQ.S", FLD: "FLD", FLE_D: "FLE.D", FLE_H: "FLE.H", FLE_Q: "FLE.Q", FLE_S: "FLE.S", FLH: "FLH", FLQ: "FLQ", FLT_D: "FLT.D", FLT_H: "FLT.H", FLT_Q: "FLT.Q", FLT_S: "FLT.S", FLW: "FLW", FMADD_D: "FMADD.D", FMADD_H: "FMADD.H", FMADD_Q: "FMADD.Q", FMADD_S: "FMADD.S", FMAX_D: "FMAX.D", FMAX_H: "FMAX.H", FMAX_Q: "FMAX.Q", FMAX_S: "FMAX.S", FMIN_D: "FMIN.D", FMIN_H: "FMIN.H", FMIN_Q: "FMIN.Q", FMIN_S: "FMIN.S", FMSUB_D: "FMSUB.D", FMSUB_H: "FMSUB.H", FMSUB_Q: "FMSUB.Q", FMSUB_S: "FMSUB.S", FMUL_D: "FMUL.D", FMUL_H: "FMUL.H", FMUL_Q: "FMUL.Q", FMUL_S: "FMUL.S", FMV_D_X: "FMV.D.X", FMV_H_X: "FMV.H.X", FMV_W_X: "FMV.W.X", FMV_X_D: "FMV.X.D", FMV_X_H: "FMV.X.H", FMV_X_W: "FMV.X.W", FNMADD_D: "FNMADD.D", FNMADD_H: "FNMADD.H", FNMADD_Q: "FNMADD.Q", FNMADD_S: "FNMADD.S", FNMSUB_D: "FNMSUB.D", FNMSUB_H: "FNMSUB.H", FNMSUB_Q: "FNMSUB.Q", FNMSUB_S: "FNMSUB.S", FSD: "FSD", FSGNJN_D: "FSGNJN.D", FSGNJN_H: "FSGNJN.H", FSGNJN_Q: "FSGNJN.Q", FSGNJN_S: "FSGNJN.S", FSGNJX_D: "FSGNJX.D", FSGNJX_H: "FSGNJX.H", FSGNJX_Q: "FSGNJX.Q", FSGNJX_S: "FSGNJX.S", FSGNJ_D: "FSGNJ.D", FSGNJ_H: "FSGNJ.H", FSGNJ_Q: "FSGNJ.Q", FSGNJ_S: "FSGNJ.S", FSH: "FSH", FSQ: "FSQ", FSQRT_D: "FSQRT.D", FSQRT_H: "FSQRT.H", FSQRT_Q: "FSQRT.Q", FSQRT_S: "FSQRT.S", FSUB_D: "FSUB.D", FSUB_H: "FSUB.H", FSUB_Q: "FSUB.Q", FSUB_S: "FSUB.S", FSW: "FSW", JAL: "JAL", JALR: "JALR", LB: "LB", LBU: "LBU", LD: "LD", LH: "LH", LHU: "LHU", LR_D: "LR.D", LR_D_AQ: "LR.D.AQ", LR_D_AQRL: "LR.D.AQRL", LR_D_RL: "LR.D.RL", LR_W: "LR.W", LR_W_AQ: "LR.W.AQ", LR_W_AQRL: "LR.W.AQRL", LR_W_RL: "LR.W.RL", LUI: "LUI", LW: "LW", LWU: "LWU", MAX: "MAX", MAXU: "MAXU", MIN: "MIN", MINU: "MINU", MUL: "MUL", MULH: "MULH", MULHSU: "MULHSU", MULHU: "MULHU", MULW: "MULW", OR: "OR", ORC_B: "ORC.B", ORI: "ORI", ORN: "ORN", REM: "REM", REMU: "REMU", REMUW: "REMUW", REMW: "REMW", REV8: "REV8", ROL: "ROL", ROLW: "ROLW", ROR: "ROR", RORI: "RORI", RORIW: "RORIW", RORW: "RORW", SB: "SB", SC_D: "SC.D", SC_D_AQ: "SC.D.AQ", SC_D_AQRL: "SC.D.AQRL", SC_D_RL: "SC.D.RL", SC_W: "SC.W", SC_W_AQ: "SC.W.AQ", SC_W_AQRL: "SC.W.AQRL", SC_W_RL: "SC.W.RL", SD: "SD", SEXT_B: "SEXT.B", SEXT_H: "SEXT.H", SH: "SH", SH1ADD: "SH1ADD", SH1ADD_UW: "SH1ADD.UW", SH2ADD: "SH2ADD", SH2ADD_UW: "SH2ADD.UW", SH3ADD: "SH3ADD", SH3ADD_UW: "SH3ADD.UW", SLL: "SLL", SLLI: "SLLI", SLLIW: "SLLIW", SLLI_UW: "SLLI.UW", SLLW: "SLLW", SLT: "SLT", SLTI: "SLTI", SLTIU: "SLTIU", SLTU: "SLTU", SRA: "SRA", SRAI: "SRAI", SRAIW: "SRAIW", SRAW: "SRAW", SRL: "SRL", SRLI: "SRLI", SRLIW: "SRLIW", SRLW: "SRLW", SUB: "SUB", SUBW: "SUBW", SW: "SW", XNOR: "XNOR", XOR: "XOR", XORI: "XORI", ZEXT_H: "ZEXT.H", } var instFormats = [...]instFormat{ // ADD rd, rs1, rs2 {mask: 0xfe00707f, value: 0x00000033, op: ADD, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // ADDI rd, rs1, imm12 {mask: 0x0000707f, value: 0x00000013, op: ADDI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, // ADDIW rd, rs1, imm12 {mask: 0x0000707f, value: 0x0000001b, op: ADDIW, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, // ADDW rd, rs1, rs2 {mask: 0xfe00707f, value: 0x0000003b, op: ADDW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // ADD.UW rd, rs1, rs2 {mask: 0xfe00707f, value: 0x0800003b, op: ADD_UW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // AMOADD.D rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x0000302f, op: AMOADD_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOADD.D.AQ rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x0400302f, op: AMOADD_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOADD.D.AQRL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x0600302f, op: AMOADD_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOADD.D.RL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x0200302f, op: AMOADD_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOADD.W rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x0000202f, op: AMOADD_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOADD.W.AQ rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x0400202f, op: AMOADD_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOADD.W.AQRL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x0600202f, op: AMOADD_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOADD.W.RL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x0200202f, op: AMOADD_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOAND.D rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x6000302f, op: AMOAND_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOAND.D.AQ rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x6400302f, op: AMOAND_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOAND.D.AQRL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x6600302f, op: AMOAND_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOAND.D.RL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x6200302f, op: AMOAND_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOAND.W rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x6000202f, op: AMOAND_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOAND.W.AQ rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x6400202f, op: AMOAND_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOAND.W.AQRL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x6600202f, op: AMOAND_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOAND.W.RL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x6200202f, op: AMOAND_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMAXU.D rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xe000302f, op: AMOMAXU_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMAXU.D.AQ rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xe400302f, op: AMOMAXU_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMAXU.D.AQRL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xe600302f, op: AMOMAXU_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMAXU.D.RL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xe200302f, op: AMOMAXU_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMAXU.W rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xe000202f, op: AMOMAXU_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMAXU.W.AQ rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xe400202f, op: AMOMAXU_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMAXU.W.AQRL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xe600202f, op: AMOMAXU_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMAXU.W.RL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xe200202f, op: AMOMAXU_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMAX.D rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xa000302f, op: AMOMAX_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMAX.D.AQ rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xa400302f, op: AMOMAX_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMAX.D.AQRL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xa600302f, op: AMOMAX_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMAX.D.RL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xa200302f, op: AMOMAX_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMAX.W rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xa000202f, op: AMOMAX_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMAX.W.AQ rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xa400202f, op: AMOMAX_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMAX.W.AQRL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xa600202f, op: AMOMAX_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMAX.W.RL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xa200202f, op: AMOMAX_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMINU.D rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xc000302f, op: AMOMINU_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMINU.D.AQ rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xc400302f, op: AMOMINU_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMINU.D.AQRL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xc600302f, op: AMOMINU_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMINU.D.RL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xc200302f, op: AMOMINU_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMINU.W rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xc000202f, op: AMOMINU_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMINU.W.AQ rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xc400202f, op: AMOMINU_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMINU.W.AQRL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xc600202f, op: AMOMINU_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMINU.W.RL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0xc200202f, op: AMOMINU_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMIN.D rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x8000302f, op: AMOMIN_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMIN.D.AQ rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x8400302f, op: AMOMIN_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMIN.D.AQRL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x8600302f, op: AMOMIN_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMIN.D.RL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x8200302f, op: AMOMIN_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMIN.W rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x8000202f, op: AMOMIN_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMIN.W.AQ rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x8400202f, op: AMOMIN_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMIN.W.AQRL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x8600202f, op: AMOMIN_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOMIN.W.RL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x8200202f, op: AMOMIN_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOOR.D rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x4000302f, op: AMOOR_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOOR.D.AQ rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x4400302f, op: AMOOR_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOOR.D.AQRL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x4600302f, op: AMOOR_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOOR.D.RL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x4200302f, op: AMOOR_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOOR.W rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x4000202f, op: AMOOR_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOOR.W.AQ rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x4400202f, op: AMOOR_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOOR.W.AQRL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x4600202f, op: AMOOR_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOOR.W.RL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x4200202f, op: AMOOR_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOSWAP.D rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x0800302f, op: AMOSWAP_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOSWAP.D.AQ rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x0c00302f, op: AMOSWAP_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOSWAP.D.AQRL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x0e00302f, op: AMOSWAP_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOSWAP.D.RL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x0a00302f, op: AMOSWAP_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOSWAP.W rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x0800202f, op: AMOSWAP_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOSWAP.W.AQ rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x0c00202f, op: AMOSWAP_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOSWAP.W.AQRL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x0e00202f, op: AMOSWAP_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOSWAP.W.RL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x0a00202f, op: AMOSWAP_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOXOR.D rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x2000302f, op: AMOXOR_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOXOR.D.AQ rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x2400302f, op: AMOXOR_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOXOR.D.AQRL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x2600302f, op: AMOXOR_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOXOR.D.RL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x2200302f, op: AMOXOR_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOXOR.W rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x2000202f, op: AMOXOR_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOXOR.W.AQ rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x2400202f, op: AMOXOR_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOXOR.W.AQRL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x2600202f, op: AMOXOR_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AMOXOR.W.RL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x2200202f, op: AMOXOR_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // AND rd, rs1, rs2 {mask: 0xfe00707f, value: 0x00007033, op: AND, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // ANDI rd, rs1, imm12 {mask: 0x0000707f, value: 0x00007013, op: ANDI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, // ANDN rd, rs1, rs2 {mask: 0xfe00707f, value: 0x40007033, op: ANDN, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // AUIPC rd, imm20 {mask: 0x0000007f, value: 0x00000017, op: AUIPC, args: argTypeList{arg_rd, arg_imm20}}, // BCLR rd, rs1, rs2 {mask: 0xfe00707f, value: 0x48001033, op: BCLR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // BCLRI rd, rs1, shamt6 {mask: 0xfc00707f, value: 0x48001013, op: BCLRI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, // BEQ rs1, rs2, bimm12 {mask: 0x0000707f, value: 0x00000063, op: BEQ, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}}, // BEXT rd, rs1, rs2 {mask: 0xfe00707f, value: 0x48005033, op: BEXT, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // BEXTI rd, rs1, shamt6 {mask: 0xfc00707f, value: 0x48005013, op: BEXTI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, // BGE rs1, rs2, bimm12 {mask: 0x0000707f, value: 0x00005063, op: BGE, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}}, // BGEU rs1, rs2, bimm12 {mask: 0x0000707f, value: 0x00007063, op: BGEU, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}}, // BINV rd, rs1, rs2 {mask: 0xfe00707f, value: 0x68001033, op: BINV, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // BINVI rd, rs1, shamt6 {mask: 0xfc00707f, value: 0x68001013, op: BINVI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, // BLT rs1, rs2, bimm12 {mask: 0x0000707f, value: 0x00004063, op: BLT, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}}, // BLTU rs1, rs2, bimm12 {mask: 0x0000707f, value: 0x00006063, op: BLTU, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}}, // BNE rs1, rs2, bimm12 {mask: 0x0000707f, value: 0x00001063, op: BNE, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}}, // BSET rd, rs1, rs2 {mask: 0xfe00707f, value: 0x28001033, op: BSET, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // BSETI rd, rs1, shamt6 {mask: 0xfc00707f, value: 0x28001013, op: BSETI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, // CLZ rd, rs1 {mask: 0xfff0707f, value: 0x60001013, op: CLZ, args: argTypeList{arg_rd, arg_rs1}}, // CLZW rd, rs1 {mask: 0xfff0707f, value: 0x6000101b, op: CLZW, args: argTypeList{arg_rd, arg_rs1}}, // CPOP rd, rs1 {mask: 0xfff0707f, value: 0x60201013, op: CPOP, args: argTypeList{arg_rd, arg_rs1}}, // CPOPW rd, rs1 {mask: 0xfff0707f, value: 0x6020101b, op: CPOPW, args: argTypeList{arg_rd, arg_rs1}}, // CSRRC rd, csr, rs1 {mask: 0x0000707f, value: 0x00003073, op: CSRRC, args: argTypeList{arg_rd, arg_csr, arg_rs1}}, // CSRRCI rd, csr, zimm {mask: 0x0000707f, value: 0x00007073, op: CSRRCI, args: argTypeList{arg_rd, arg_csr, arg_zimm}}, // CSRRS rd, csr, rs1 {mask: 0x0000707f, value: 0x00002073, op: CSRRS, args: argTypeList{arg_rd, arg_csr, arg_rs1}}, // CSRRSI rd, csr, zimm {mask: 0x0000707f, value: 0x00006073, op: CSRRSI, args: argTypeList{arg_rd, arg_csr, arg_zimm}}, // CSRRW rd, csr, rs1 {mask: 0x0000707f, value: 0x00001073, op: CSRRW, args: argTypeList{arg_rd, arg_csr, arg_rs1}}, // CSRRWI rd, csr, zimm {mask: 0x0000707f, value: 0x00005073, op: CSRRWI, args: argTypeList{arg_rd, arg_csr, arg_zimm}}, // CTZ rd, rs1 {mask: 0xfff0707f, value: 0x60101013, op: CTZ, args: argTypeList{arg_rd, arg_rs1}}, // CTZW rd, rs1 {mask: 0xfff0707f, value: 0x6010101b, op: CTZW, args: argTypeList{arg_rd, arg_rs1}}, // C.ADD rd_rs1_n0, c_rs2_n0 {mask: 0x0000f003, value: 0x00009002, op: C_ADD, args: argTypeList{arg_rd_rs1_n0, arg_c_rs2_n0}}, // C.ADDI rd_rs1_n0, c_nzimm6 {mask: 0x0000e003, value: 0x00000001, op: C_ADDI, args: argTypeList{arg_rd_rs1_n0, arg_c_nzimm6}}, // C.ADDI16SP c_nzimm10 {mask: 0x0000ef83, value: 0x00006101, op: C_ADDI16SP, args: argTypeList{arg_c_nzimm10}}, // C.ADDI4SPN rd_p, c_nzuimm10 {mask: 0x0000e003, value: 0x00000000, op: C_ADDI4SPN, args: argTypeList{arg_rd_p, arg_c_nzuimm10}}, // C.ADDIW rd_rs1_n0, c_imm6 {mask: 0x0000e003, value: 0x00002001, op: C_ADDIW, args: argTypeList{arg_rd_rs1_n0, arg_c_imm6}}, // C.ADDW rd_rs1_p, rs2_p {mask: 0x0000fc63, value: 0x00009c21, op: C_ADDW, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}}, // C.AND rd_rs1_p, rs2_p {mask: 0x0000fc63, value: 0x00008c61, op: C_AND, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}}, // C.ANDI rd_rs1_p, c_imm6 {mask: 0x0000ec03, value: 0x00008801, op: C_ANDI, args: argTypeList{arg_rd_rs1_p, arg_c_imm6}}, // C.BEQZ rs1_p, c_bimm9 {mask: 0x0000e003, value: 0x0000c001, op: C_BEQZ, args: argTypeList{arg_rs1_p, arg_c_bimm9}}, // C.BNEZ rs1_p, c_bimm9 {mask: 0x0000e003, value: 0x0000e001, op: C_BNEZ, args: argTypeList{arg_rs1_p, arg_c_bimm9}}, // C.EBREAK {mask: 0x0000ffff, value: 0x00009002, op: C_EBREAK, args: argTypeList{}}, // C.FLD fd_p, rs1_p, c_uimm8 {mask: 0x0000e003, value: 0x00002000, op: C_FLD, args: argTypeList{arg_fd_p, arg_rs1_p, arg_c_uimm8}}, // C.FLDSP fd, c_uimm9sp {mask: 0x0000e003, value: 0x00002002, op: C_FLDSP, args: argTypeList{arg_fd, arg_c_uimm9sp}}, // C.FSD rs1_p, fs2_p, c_uimm8 {mask: 0x0000e003, value: 0x0000a000, op: C_FSD, args: argTypeList{arg_rs1_p, arg_fs2_p, arg_c_uimm8}}, // C.FSDSP c_fs2, c_uimm9sp_s {mask: 0x0000e003, value: 0x0000a002, op: C_FSDSP, args: argTypeList{arg_c_fs2, arg_c_uimm9sp_s}}, // C.J c_imm12 {mask: 0x0000e003, value: 0x0000a001, op: C_J, args: argTypeList{arg_c_imm12}}, // C.JALR c_rs1_n0 {mask: 0x0000f07f, value: 0x00009002, op: C_JALR, args: argTypeList{arg_c_rs1_n0}}, // C.JR rs1_n0 {mask: 0x0000f07f, value: 0x00008002, op: C_JR, args: argTypeList{arg_rs1_n0}}, // C.LD rd_p, rs1_p, c_uimm8 {mask: 0x0000e003, value: 0x00006000, op: C_LD, args: argTypeList{arg_rd_p, arg_rs1_p, arg_c_uimm8}}, // C.LDSP rd_n0, c_uimm9sp {mask: 0x0000e003, value: 0x00006002, op: C_LDSP, args: argTypeList{arg_rd_n0, arg_c_uimm9sp}}, // C.LI rd_n0, c_imm6 {mask: 0x0000e003, value: 0x00004001, op: C_LI, args: argTypeList{arg_rd_n0, arg_c_imm6}}, // C.LUI rd_n2, c_nzimm18 {mask: 0x0000e003, value: 0x00006001, op: C_LUI, args: argTypeList{arg_rd_n2, arg_c_nzimm18}}, // C.LW rd_p, rs1_p, c_uimm7 {mask: 0x0000e003, value: 0x00004000, op: C_LW, args: argTypeList{arg_rd_p, arg_rs1_p, arg_c_uimm7}}, // C.LWSP rd_n0, c_uimm8sp {mask: 0x0000e003, value: 0x00004002, op: C_LWSP, args: argTypeList{arg_rd_n0, arg_c_uimm8sp}}, // C.MV rd_n0, c_rs2_n0 {mask: 0x0000f003, value: 0x00008002, op: C_MV, args: argTypeList{arg_rd_n0, arg_c_rs2_n0}}, // C.NOP c_nzimm6 {mask: 0x0000ef83, value: 0x00000001, op: C_NOP, args: argTypeList{arg_c_nzimm6}}, // C.OR rd_rs1_p, rs2_p {mask: 0x0000fc63, value: 0x00008c41, op: C_OR, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}}, // C.SD rs1_p, rs2_p, c_uimm8 {mask: 0x0000e003, value: 0x0000e000, op: C_SD, args: argTypeList{arg_rs1_p, arg_rs2_p, arg_c_uimm8}}, // C.SDSP c_rs2, c_uimm9sp_s {mask: 0x0000e003, value: 0x0000e002, op: C_SDSP, args: argTypeList{arg_c_rs2, arg_c_uimm9sp_s}}, // C.SLLI rd_rs1_n0, c_nzuimm6 {mask: 0x0000e003, value: 0x00000002, op: C_SLLI, args: argTypeList{arg_rd_rs1_n0, arg_c_nzuimm6}}, // C.SRAI rd_rs1_p, c_nzuimm6 {mask: 0x0000ec03, value: 0x00008401, op: C_SRAI, args: argTypeList{arg_rd_rs1_p, arg_c_nzuimm6}}, // C.SRLI rd_rs1_p, c_nzuimm6 {mask: 0x0000ec03, value: 0x00008001, op: C_SRLI, args: argTypeList{arg_rd_rs1_p, arg_c_nzuimm6}}, // C.SUB rd_rs1_p, rs2_p {mask: 0x0000fc63, value: 0x00008c01, op: C_SUB, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}}, // C.SUBW rd_rs1_p, rs2_p {mask: 0x0000fc63, value: 0x00009c01, op: C_SUBW, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}}, // C.SW rs1_p, rs2_p, c_uimm7 {mask: 0x0000e003, value: 0x0000c000, op: C_SW, args: argTypeList{arg_rs1_p, arg_rs2_p, arg_c_uimm7}}, // C.SWSP c_rs2, c_uimm8sp_s {mask: 0x0000e003, value: 0x0000c002, op: C_SWSP, args: argTypeList{arg_c_rs2, arg_c_uimm8sp_s}}, // C.UNIMP {mask: 0x0000ffff, value: 0x00000000, op: C_UNIMP, args: argTypeList{}}, // C.XOR rd_rs1_p, rs2_p {mask: 0x0000fc63, value: 0x00008c21, op: C_XOR, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}}, // DIV rd, rs1, rs2 {mask: 0xfe00707f, value: 0x02004033, op: DIV, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // DIVU rd, rs1, rs2 {mask: 0xfe00707f, value: 0x02005033, op: DIVU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // DIVUW rd, rs1, rs2 {mask: 0xfe00707f, value: 0x0200503b, op: DIVUW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // DIVW rd, rs1, rs2 {mask: 0xfe00707f, value: 0x0200403b, op: DIVW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // EBREAK {mask: 0xffffffff, value: 0x00100073, op: EBREAK, args: argTypeList{}}, // ECALL {mask: 0xffffffff, value: 0x00000073, op: ECALL, args: argTypeList{}}, // FADD.D fd, fs1, fs2 {mask: 0xfe00007f, value: 0x02000053, op: FADD_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FADD.H fd, fs1, fs2 {mask: 0xfe00007f, value: 0x04000053, op: FADD_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FADD.Q fd, fs1, fs2 {mask: 0xfe00007f, value: 0x06000053, op: FADD_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FADD.S fd, fs1, fs2 {mask: 0xfe00007f, value: 0x00000053, op: FADD_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FCLASS.D rd, fs1 {mask: 0xfff0707f, value: 0xe2001053, op: FCLASS_D, args: argTypeList{arg_rd, arg_fs1}}, // FCLASS.H rd, fs1 {mask: 0xfff0707f, value: 0xe4001053, op: FCLASS_H, args: argTypeList{arg_rd, arg_fs1}}, // FCLASS.Q rd, fs1 {mask: 0xfff0707f, value: 0xe6001053, op: FCLASS_Q, args: argTypeList{arg_rd, arg_fs1}}, // FCLASS.S rd, fs1 {mask: 0xfff0707f, value: 0xe0001053, op: FCLASS_S, args: argTypeList{arg_rd, arg_fs1}}, // FCVT.D.L fd, rs1 {mask: 0xfff0007f, value: 0xd2200053, op: FCVT_D_L, args: argTypeList{arg_fd, arg_rs1}}, // FCVT.D.LU fd, rs1 {mask: 0xfff0007f, value: 0xd2300053, op: FCVT_D_LU, args: argTypeList{arg_fd, arg_rs1}}, // FCVT.D.Q fd, fs1 {mask: 0xfff0007f, value: 0x42300053, op: FCVT_D_Q, args: argTypeList{arg_fd, arg_fs1}}, // FCVT.D.S fd, fs1 {mask: 0xfff0007f, value: 0x42000053, op: FCVT_D_S, args: argTypeList{arg_fd, arg_fs1}}, // FCVT.D.W fd, rs1 {mask: 0xfff0007f, value: 0xd2000053, op: FCVT_D_W, args: argTypeList{arg_fd, arg_rs1}}, // FCVT.D.WU fd, rs1 {mask: 0xfff0007f, value: 0xd2100053, op: FCVT_D_WU, args: argTypeList{arg_fd, arg_rs1}}, // FCVT.H.L fd, rs1 {mask: 0xfff0007f, value: 0xd4200053, op: FCVT_H_L, args: argTypeList{arg_fd, arg_rs1}}, // FCVT.H.LU fd, rs1 {mask: 0xfff0007f, value: 0xd4300053, op: FCVT_H_LU, args: argTypeList{arg_fd, arg_rs1}}, // FCVT.H.S fd, fs1 {mask: 0xfff0007f, value: 0x44000053, op: FCVT_H_S, args: argTypeList{arg_fd, arg_fs1}}, // FCVT.H.W fd, rs1 {mask: 0xfff0007f, value: 0xd4000053, op: FCVT_H_W, args: argTypeList{arg_fd, arg_rs1}}, // FCVT.H.WU fd, rs1 {mask: 0xfff0007f, value: 0xd4100053, op: FCVT_H_WU, args: argTypeList{arg_fd, arg_rs1}}, // FCVT.LU.D rd, fs1 {mask: 0xfff0007f, value: 0xc2300053, op: FCVT_LU_D, args: argTypeList{arg_rd, arg_fs1}}, // FCVT.LU.H rd, fs1 {mask: 0xfff0007f, value: 0xc4300053, op: FCVT_LU_H, args: argTypeList{arg_rd, arg_fs1}}, // FCVT.LU.Q rd, fs1 {mask: 0xfff0007f, value: 0xc6300053, op: FCVT_LU_Q, args: argTypeList{arg_rd, arg_fs1}}, // FCVT.LU.S rd, fs1 {mask: 0xfff0007f, value: 0xc0300053, op: FCVT_LU_S, args: argTypeList{arg_rd, arg_fs1}}, // FCVT.L.D rd, fs1 {mask: 0xfff0007f, value: 0xc2200053, op: FCVT_L_D, args: argTypeList{arg_rd, arg_fs1}}, // FCVT.L.H rd, fs1 {mask: 0xfff0007f, value: 0xc4200053, op: FCVT_L_H, args: argTypeList{arg_rd, arg_fs1}}, // FCVT.L.Q rd, fs1 {mask: 0xfff0007f, value: 0xc6200053, op: FCVT_L_Q, args: argTypeList{arg_rd, arg_fs1}}, // FCVT.L.S rd, fs1 {mask: 0xfff0007f, value: 0xc0200053, op: FCVT_L_S, args: argTypeList{arg_rd, arg_fs1}}, // FCVT.Q.D fd, fs1 {mask: 0xfff0007f, value: 0x46100053, op: FCVT_Q_D, args: argTypeList{arg_fd, arg_fs1}}, // FCVT.Q.L fd, rs1 {mask: 0xfff0007f, value: 0xd6200053, op: FCVT_Q_L, args: argTypeList{arg_fd, arg_rs1}}, // FCVT.Q.LU fd, rs1 {mask: 0xfff0007f, value: 0xd6300053, op: FCVT_Q_LU, args: argTypeList{arg_fd, arg_rs1}}, // FCVT.Q.S fd, fs1 {mask: 0xfff0007f, value: 0x46000053, op: FCVT_Q_S, args: argTypeList{arg_fd, arg_fs1}}, // FCVT.Q.W fd, rs1 {mask: 0xfff0007f, value: 0xd6000053, op: FCVT_Q_W, args: argTypeList{arg_fd, arg_rs1}}, // FCVT.Q.WU fd, rs1 {mask: 0xfff0007f, value: 0xd6100053, op: FCVT_Q_WU, args: argTypeList{arg_fd, arg_rs1}}, // FCVT.S.D fd, fs1 {mask: 0xfff0007f, value: 0x40100053, op: FCVT_S_D, args: argTypeList{arg_fd, arg_fs1}}, // FCVT.S.H fd, fs1 {mask: 0xfff0007f, value: 0x40200053, op: FCVT_S_H, args: argTypeList{arg_fd, arg_fs1}}, // FCVT.S.L fd, rs1 {mask: 0xfff0007f, value: 0xd0200053, op: FCVT_S_L, args: argTypeList{arg_fd, arg_rs1}}, // FCVT.S.LU fd, rs1 {mask: 0xfff0007f, value: 0xd0300053, op: FCVT_S_LU, args: argTypeList{arg_fd, arg_rs1}}, // FCVT.S.Q fd, fs1 {mask: 0xfff0007f, value: 0x40300053, op: FCVT_S_Q, args: argTypeList{arg_fd, arg_fs1}}, // FCVT.S.W fd, rs1 {mask: 0xfff0007f, value: 0xd0000053, op: FCVT_S_W, args: argTypeList{arg_fd, arg_rs1}}, // FCVT.S.WU fd, rs1 {mask: 0xfff0007f, value: 0xd0100053, op: FCVT_S_WU, args: argTypeList{arg_fd, arg_rs1}}, // FCVT.WU.D rd, fs1 {mask: 0xfff0007f, value: 0xc2100053, op: FCVT_WU_D, args: argTypeList{arg_rd, arg_fs1}}, // FCVT.WU.H rd, fs1 {mask: 0xfff0007f, value: 0xc4100053, op: FCVT_WU_H, args: argTypeList{arg_rd, arg_fs1}}, // FCVT.WU.Q rd, fs1 {mask: 0xfff0007f, value: 0xc6100053, op: FCVT_WU_Q, args: argTypeList{arg_rd, arg_fs1}}, // FCVT.WU.S rd, fs1 {mask: 0xfff0007f, value: 0xc0100053, op: FCVT_WU_S, args: argTypeList{arg_rd, arg_fs1}}, // FCVT.W.D rd, fs1 {mask: 0xfff0007f, value: 0xc2000053, op: FCVT_W_D, args: argTypeList{arg_rd, arg_fs1}}, // FCVT.W.H rd, fs1 {mask: 0xfff0007f, value: 0xc4000053, op: FCVT_W_H, args: argTypeList{arg_rd, arg_fs1}}, // FCVT.W.Q rd, fs1 {mask: 0xfff0007f, value: 0xc6000053, op: FCVT_W_Q, args: argTypeList{arg_rd, arg_fs1}}, // FCVT.W.S rd, fs1 {mask: 0xfff0007f, value: 0xc0000053, op: FCVT_W_S, args: argTypeList{arg_rd, arg_fs1}}, // FDIV.D fd, fs1, fs2 {mask: 0xfe00007f, value: 0x1a000053, op: FDIV_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FDIV.H fd, fs1, fs2 {mask: 0xfe00007f, value: 0x1c000053, op: FDIV_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FDIV.Q fd, fs1, fs2 {mask: 0xfe00007f, value: 0x1e000053, op: FDIV_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FDIV.S fd, fs1, fs2 {mask: 0xfe00007f, value: 0x18000053, op: FDIV_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FENCE pred, succ {mask: 0x0000707f, value: 0x0000000f, op: FENCE, args: argTypeList{arg_pred, arg_succ}}, // FENCE.I {mask: 0x0000707f, value: 0x0000100f, op: FENCE_I, args: argTypeList{}}, // FEQ.D rd, fs1, fs2 {mask: 0xfe00707f, value: 0xa2002053, op: FEQ_D, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, // FEQ.H rd, fs1, fs2 {mask: 0xfe00707f, value: 0xa4002053, op: FEQ_H, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, // FEQ.Q rd, fs1, fs2 {mask: 0xfe00707f, value: 0xa6002053, op: FEQ_Q, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, // FEQ.S rd, fs1, fs2 {mask: 0xfe00707f, value: 0xa0002053, op: FEQ_S, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, // FLD fd, rs1_mem {mask: 0x0000707f, value: 0x00003007, op: FLD, args: argTypeList{arg_fd, arg_rs1_mem}}, // FLE.D rd, fs1, fs2 {mask: 0xfe00707f, value: 0xa2000053, op: FLE_D, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, // FLE.H rd, fs1, fs2 {mask: 0xfe00707f, value: 0xa4000053, op: FLE_H, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, // FLE.Q rd, fs1, fs2 {mask: 0xfe00707f, value: 0xa6000053, op: FLE_Q, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, // FLE.S rd, fs1, fs2 {mask: 0xfe00707f, value: 0xa0000053, op: FLE_S, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, // FLH fd, rs1_mem {mask: 0x0000707f, value: 0x00001007, op: FLH, args: argTypeList{arg_fd, arg_rs1_mem}}, // FLQ fd, rs1_mem {mask: 0x0000707f, value: 0x00004007, op: FLQ, args: argTypeList{arg_fd, arg_rs1_mem}}, // FLT.D rd, fs1, fs2 {mask: 0xfe00707f, value: 0xa2001053, op: FLT_D, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, // FLT.H rd, fs1, fs2 {mask: 0xfe00707f, value: 0xa4001053, op: FLT_H, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, // FLT.Q rd, fs1, fs2 {mask: 0xfe00707f, value: 0xa6001053, op: FLT_Q, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, // FLT.S rd, fs1, fs2 {mask: 0xfe00707f, value: 0xa0001053, op: FLT_S, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, // FLW fd, rs1_mem {mask: 0x0000707f, value: 0x00002007, op: FLW, args: argTypeList{arg_fd, arg_rs1_mem}}, // FMADD.D fd, fs1, fs2, fs3 {mask: 0x0600007f, value: 0x02000043, op: FMADD_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, // FMADD.H fd, fs1, fs2, fs3 {mask: 0x0600007f, value: 0x04000043, op: FMADD_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, // FMADD.Q fd, fs1, fs2, fs3 {mask: 0x0600007f, value: 0x06000043, op: FMADD_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, // FMADD.S fd, fs1, fs2, fs3 {mask: 0x0600007f, value: 0x00000043, op: FMADD_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, // FMAX.D fd, fs1, fs2 {mask: 0xfe00707f, value: 0x2a001053, op: FMAX_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FMAX.H fd, fs1, fs2 {mask: 0xfe00707f, value: 0x2c001053, op: FMAX_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FMAX.Q fd, fs1, fs2 {mask: 0xfe00707f, value: 0x2e001053, op: FMAX_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FMAX.S fd, fs1, fs2 {mask: 0xfe00707f, value: 0x28001053, op: FMAX_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FMIN.D fd, fs1, fs2 {mask: 0xfe00707f, value: 0x2a000053, op: FMIN_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FMIN.H fd, fs1, fs2 {mask: 0xfe00707f, value: 0x2c000053, op: FMIN_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FMIN.Q fd, fs1, fs2 {mask: 0xfe00707f, value: 0x2e000053, op: FMIN_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FMIN.S fd, fs1, fs2 {mask: 0xfe00707f, value: 0x28000053, op: FMIN_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FMSUB.D fd, fs1, fs2, fs3 {mask: 0x0600007f, value: 0x02000047, op: FMSUB_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, // FMSUB.H fd, fs1, fs2, fs3 {mask: 0x0600007f, value: 0x04000047, op: FMSUB_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, // FMSUB.Q fd, fs1, fs2, fs3 {mask: 0x0600007f, value: 0x06000047, op: FMSUB_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, // FMSUB.S fd, fs1, fs2, fs3 {mask: 0x0600007f, value: 0x00000047, op: FMSUB_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, // FMUL.D fd, fs1, fs2 {mask: 0xfe00007f, value: 0x12000053, op: FMUL_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FMUL.H fd, fs1, fs2 {mask: 0xfe00007f, value: 0x14000053, op: FMUL_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FMUL.Q fd, fs1, fs2 {mask: 0xfe00007f, value: 0x16000053, op: FMUL_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FMUL.S fd, fs1, fs2 {mask: 0xfe00007f, value: 0x10000053, op: FMUL_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FMV.D.X fd, rs1 {mask: 0xfff0707f, value: 0xf2000053, op: FMV_D_X, args: argTypeList{arg_fd, arg_rs1}}, // FMV.H.X fd, rs1 {mask: 0xfff0707f, value: 0xf4000053, op: FMV_H_X, args: argTypeList{arg_fd, arg_rs1}}, // FMV.W.X fd, rs1 {mask: 0xfff0707f, value: 0xf0000053, op: FMV_W_X, args: argTypeList{arg_fd, arg_rs1}}, // FMV.X.D rd, fs1 {mask: 0xfff0707f, value: 0xe2000053, op: FMV_X_D, args: argTypeList{arg_rd, arg_fs1}}, // FMV.X.H rd, fs1 {mask: 0xfff0707f, value: 0xe4000053, op: FMV_X_H, args: argTypeList{arg_rd, arg_fs1}}, // FMV.X.W rd, fs1 {mask: 0xfff0707f, value: 0xe0000053, op: FMV_X_W, args: argTypeList{arg_rd, arg_fs1}}, // FNMADD.D fd, fs1, fs2, fs3 {mask: 0x0600007f, value: 0x0200004f, op: FNMADD_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, // FNMADD.H fd, fs1, fs2, fs3 {mask: 0x0600007f, value: 0x0400004f, op: FNMADD_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, // FNMADD.Q fd, fs1, fs2, fs3 {mask: 0x0600007f, value: 0x0600004f, op: FNMADD_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, // FNMADD.S fd, fs1, fs2, fs3 {mask: 0x0600007f, value: 0x0000004f, op: FNMADD_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, // FNMSUB.D fd, fs1, fs2, fs3 {mask: 0x0600007f, value: 0x0200004b, op: FNMSUB_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, // FNMSUB.H fd, fs1, fs2, fs3 {mask: 0x0600007f, value: 0x0400004b, op: FNMSUB_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, // FNMSUB.Q fd, fs1, fs2, fs3 {mask: 0x0600007f, value: 0x0600004b, op: FNMSUB_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, // FNMSUB.S fd, fs1, fs2, fs3 {mask: 0x0600007f, value: 0x0000004b, op: FNMSUB_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, // FSD fs2, rs1_store {mask: 0x0000707f, value: 0x00003027, op: FSD, args: argTypeList{arg_fs2, arg_rs1_store}}, // FSGNJN.D fd, fs1, fs2 {mask: 0xfe00707f, value: 0x22001053, op: FSGNJN_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FSGNJN.H fd, fs1, fs2 {mask: 0xfe00707f, value: 0x24001053, op: FSGNJN_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FSGNJN.Q fd, fs1, fs2 {mask: 0xfe00707f, value: 0x26001053, op: FSGNJN_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FSGNJN.S fd, fs1, fs2 {mask: 0xfe00707f, value: 0x20001053, op: FSGNJN_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FSGNJX.D fd, fs1, fs2 {mask: 0xfe00707f, value: 0x22002053, op: FSGNJX_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FSGNJX.H fd, fs1, fs2 {mask: 0xfe00707f, value: 0x24002053, op: FSGNJX_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FSGNJX.Q fd, fs1, fs2 {mask: 0xfe00707f, value: 0x26002053, op: FSGNJX_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FSGNJX.S fd, fs1, fs2 {mask: 0xfe00707f, value: 0x20002053, op: FSGNJX_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FSGNJ.D fd, fs1, fs2 {mask: 0xfe00707f, value: 0x22000053, op: FSGNJ_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FSGNJ.H fd, fs1, fs2 {mask: 0xfe00707f, value: 0x24000053, op: FSGNJ_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FSGNJ.Q fd, fs1, fs2 {mask: 0xfe00707f, value: 0x26000053, op: FSGNJ_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FSGNJ.S fd, fs1, fs2 {mask: 0xfe00707f, value: 0x20000053, op: FSGNJ_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FSH fs2, rs1_store {mask: 0x0000707f, value: 0x00001027, op: FSH, args: argTypeList{arg_fs2, arg_rs1_store}}, // FSQ fs2, rs1_store {mask: 0x0000707f, value: 0x00004027, op: FSQ, args: argTypeList{arg_fs2, arg_rs1_store}}, // FSQRT.D fd, fs1 {mask: 0xfff0007f, value: 0x5a000053, op: FSQRT_D, args: argTypeList{arg_fd, arg_fs1}}, // FSQRT.H fd, fs1 {mask: 0xfff0007f, value: 0x5c000053, op: FSQRT_H, args: argTypeList{arg_fd, arg_fs1}}, // FSQRT.Q fd, fs1 {mask: 0xfff0007f, value: 0x5e000053, op: FSQRT_Q, args: argTypeList{arg_fd, arg_fs1}}, // FSQRT.S fd, fs1 {mask: 0xfff0007f, value: 0x58000053, op: FSQRT_S, args: argTypeList{arg_fd, arg_fs1}}, // FSUB.D fd, fs1, fs2 {mask: 0xfe00007f, value: 0x0a000053, op: FSUB_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FSUB.H fd, fs1, fs2 {mask: 0xfe00007f, value: 0x0c000053, op: FSUB_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FSUB.Q fd, fs1, fs2 {mask: 0xfe00007f, value: 0x0e000053, op: FSUB_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FSUB.S fd, fs1, fs2 {mask: 0xfe00007f, value: 0x08000053, op: FSUB_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, // FSW fs2, rs1_store {mask: 0x0000707f, value: 0x00002027, op: FSW, args: argTypeList{arg_fs2, arg_rs1_store}}, // JAL rd, jimm20 {mask: 0x0000007f, value: 0x0000006f, op: JAL, args: argTypeList{arg_rd, arg_jimm20}}, // JALR rd, rs1_mem {mask: 0x0000707f, value: 0x00000067, op: JALR, args: argTypeList{arg_rd, arg_rs1_mem}}, // LB rd, rs1_mem {mask: 0x0000707f, value: 0x00000003, op: LB, args: argTypeList{arg_rd, arg_rs1_mem}}, // LBU rd, rs1_mem {mask: 0x0000707f, value: 0x00004003, op: LBU, args: argTypeList{arg_rd, arg_rs1_mem}}, // LD rd, rs1_mem {mask: 0x0000707f, value: 0x00003003, op: LD, args: argTypeList{arg_rd, arg_rs1_mem}}, // LH rd, rs1_mem {mask: 0x0000707f, value: 0x00001003, op: LH, args: argTypeList{arg_rd, arg_rs1_mem}}, // LHU rd, rs1_mem {mask: 0x0000707f, value: 0x00005003, op: LHU, args: argTypeList{arg_rd, arg_rs1_mem}}, // LR.D rd, rs1_amo {mask: 0xfff0707f, value: 0x1000302f, op: LR_D, args: argTypeList{arg_rd, arg_rs1_amo}}, // LR.D.AQ rd, rs1_amo {mask: 0xfff0707f, value: 0x1400302f, op: LR_D_AQ, args: argTypeList{arg_rd, arg_rs1_amo}}, // LR.D.AQRL rd, rs1_amo {mask: 0xfff0707f, value: 0x1600302f, op: LR_D_AQRL, args: argTypeList{arg_rd, arg_rs1_amo}}, // LR.D.RL rd, rs1_amo {mask: 0xfff0707f, value: 0x1200302f, op: LR_D_RL, args: argTypeList{arg_rd, arg_rs1_amo}}, // LR.W rd, rs1_amo {mask: 0xfff0707f, value: 0x1000202f, op: LR_W, args: argTypeList{arg_rd, arg_rs1_amo}}, // LR.W.AQ rd, rs1_amo {mask: 0xfff0707f, value: 0x1400202f, op: LR_W_AQ, args: argTypeList{arg_rd, arg_rs1_amo}}, // LR.W.AQRL rd, rs1_amo {mask: 0xfff0707f, value: 0x1600202f, op: LR_W_AQRL, args: argTypeList{arg_rd, arg_rs1_amo}}, // LR.W.RL rd, rs1_amo {mask: 0xfff0707f, value: 0x1200202f, op: LR_W_RL, args: argTypeList{arg_rd, arg_rs1_amo}}, // LUI rd, imm20 {mask: 0x0000007f, value: 0x00000037, op: LUI, args: argTypeList{arg_rd, arg_imm20}}, // LW rd, rs1_mem {mask: 0x0000707f, value: 0x00002003, op: LW, args: argTypeList{arg_rd, arg_rs1_mem}}, // LWU rd, rs1_mem {mask: 0x0000707f, value: 0x00006003, op: LWU, args: argTypeList{arg_rd, arg_rs1_mem}}, // MAX rd, rs1, rs2 {mask: 0xfe00707f, value: 0x0a006033, op: MAX, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // MAXU rd, rs1, rs2 {mask: 0xfe00707f, value: 0x0a007033, op: MAXU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // MIN rd, rs1, rs2 {mask: 0xfe00707f, value: 0x0a004033, op: MIN, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // MINU rd, rs1, rs2 {mask: 0xfe00707f, value: 0x0a005033, op: MINU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // MUL rd, rs1, rs2 {mask: 0xfe00707f, value: 0x02000033, op: MUL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // MULH rd, rs1, rs2 {mask: 0xfe00707f, value: 0x02001033, op: MULH, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // MULHSU rd, rs1, rs2 {mask: 0xfe00707f, value: 0x02002033, op: MULHSU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // MULHU rd, rs1, rs2 {mask: 0xfe00707f, value: 0x02003033, op: MULHU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // MULW rd, rs1, rs2 {mask: 0xfe00707f, value: 0x0200003b, op: MULW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // OR rd, rs1, rs2 {mask: 0xfe00707f, value: 0x00006033, op: OR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // ORC.B rd, rs1 {mask: 0xfff0707f, value: 0x28705013, op: ORC_B, args: argTypeList{arg_rd, arg_rs1}}, // ORI rd, rs1, imm12 {mask: 0x0000707f, value: 0x00006013, op: ORI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, // ORN rd, rs1, rs2 {mask: 0xfe00707f, value: 0x40006033, op: ORN, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // REM rd, rs1, rs2 {mask: 0xfe00707f, value: 0x02006033, op: REM, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // REMU rd, rs1, rs2 {mask: 0xfe00707f, value: 0x02007033, op: REMU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // REMUW rd, rs1, rs2 {mask: 0xfe00707f, value: 0x0200703b, op: REMUW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // REMW rd, rs1, rs2 {mask: 0xfe00707f, value: 0x0200603b, op: REMW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // REV8 rd, rs1 {mask: 0xfff0707f, value: 0x6b805013, op: REV8, args: argTypeList{arg_rd, arg_rs1}}, // ROL rd, rs1, rs2 {mask: 0xfe00707f, value: 0x60001033, op: ROL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // ROLW rd, rs1, rs2 {mask: 0xfe00707f, value: 0x6000103b, op: ROLW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // ROR rd, rs1, rs2 {mask: 0xfe00707f, value: 0x60005033, op: ROR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // RORI rd, rs1, shamt6 {mask: 0xfc00707f, value: 0x60005013, op: RORI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, // RORIW rd, rs1, shamt5 {mask: 0xfe00707f, value: 0x6000501b, op: RORIW, args: argTypeList{arg_rd, arg_rs1, arg_shamt5}}, // RORW rd, rs1, rs2 {mask: 0xfe00707f, value: 0x6000503b, op: RORW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // SB rs2, rs1_store {mask: 0x0000707f, value: 0x00000023, op: SB, args: argTypeList{arg_rs2, arg_rs1_store}}, // SC.D rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x1800302f, op: SC_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // SC.D.AQ rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x1c00302f, op: SC_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // SC.D.AQRL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x1e00302f, op: SC_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // SC.D.RL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x1a00302f, op: SC_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // SC.W rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x1800202f, op: SC_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // SC.W.AQ rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x1c00202f, op: SC_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // SC.W.AQRL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x1e00202f, op: SC_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // SC.W.RL rd, rs2, rs1_amo {mask: 0xfe00707f, value: 0x1a00202f, op: SC_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, // SD rs2, rs1_store {mask: 0x0000707f, value: 0x00003023, op: SD, args: argTypeList{arg_rs2, arg_rs1_store}}, // SEXT.B rd, rs1 {mask: 0xfff0707f, value: 0x60401013, op: SEXT_B, args: argTypeList{arg_rd, arg_rs1}}, // SEXT.H rd, rs1 {mask: 0xfff0707f, value: 0x60501013, op: SEXT_H, args: argTypeList{arg_rd, arg_rs1}}, // SH rs2, rs1_store {mask: 0x0000707f, value: 0x00001023, op: SH, args: argTypeList{arg_rs2, arg_rs1_store}}, // SH1ADD rd, rs1, rs2 {mask: 0xfe00707f, value: 0x20002033, op: SH1ADD, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // SH1ADD.UW rd, rs1, rs2 {mask: 0xfe00707f, value: 0x2000203b, op: SH1ADD_UW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // SH2ADD rd, rs1, rs2 {mask: 0xfe00707f, value: 0x20004033, op: SH2ADD, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // SH2ADD.UW rd, rs1, rs2 {mask: 0xfe00707f, value: 0x2000403b, op: SH2ADD_UW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // SH3ADD rd, rs1, rs2 {mask: 0xfe00707f, value: 0x20006033, op: SH3ADD, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // SH3ADD.UW rd, rs1, rs2 {mask: 0xfe00707f, value: 0x2000603b, op: SH3ADD_UW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // SLL rd, rs1, rs2 {mask: 0xfe00707f, value: 0x00001033, op: SLL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // SLLI rd, rs1, shamt6 {mask: 0xfc00707f, value: 0x00001013, op: SLLI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, // SLLIW rd, rs1, shamt5 {mask: 0xfe00707f, value: 0x0000101b, op: SLLIW, args: argTypeList{arg_rd, arg_rs1, arg_shamt5}}, // SLLI.UW rd, rs1, shamt6 {mask: 0xfc00707f, value: 0x0800101b, op: SLLI_UW, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, // SLLW rd, rs1, rs2 {mask: 0xfe00707f, value: 0x0000103b, op: SLLW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // SLT rd, rs1, rs2 {mask: 0xfe00707f, value: 0x00002033, op: SLT, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // SLTI rd, rs1, imm12 {mask: 0x0000707f, value: 0x00002013, op: SLTI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, // SLTIU rd, rs1, imm12 {mask: 0x0000707f, value: 0x00003013, op: SLTIU, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, // SLTU rd, rs1, rs2 {mask: 0xfe00707f, value: 0x00003033, op: SLTU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // SRA rd, rs1, rs2 {mask: 0xfe00707f, value: 0x40005033, op: SRA, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // SRAI rd, rs1, shamt6 {mask: 0xfc00707f, value: 0x40005013, op: SRAI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, // SRAIW rd, rs1, shamt5 {mask: 0xfe00707f, value: 0x4000501b, op: SRAIW, args: argTypeList{arg_rd, arg_rs1, arg_shamt5}}, // SRAW rd, rs1, rs2 {mask: 0xfe00707f, value: 0x4000503b, op: SRAW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // SRL rd, rs1, rs2 {mask: 0xfe00707f, value: 0x00005033, op: SRL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // SRLI rd, rs1, shamt6 {mask: 0xfc00707f, value: 0x00005013, op: SRLI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, // SRLIW rd, rs1, shamt5 {mask: 0xfe00707f, value: 0x0000501b, op: SRLIW, args: argTypeList{arg_rd, arg_rs1, arg_shamt5}}, // SRLW rd, rs1, rs2 {mask: 0xfe00707f, value: 0x0000503b, op: SRLW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // SUB rd, rs1, rs2 {mask: 0xfe00707f, value: 0x40000033, op: SUB, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // SUBW rd, rs1, rs2 {mask: 0xfe00707f, value: 0x4000003b, op: SUBW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // SW rs2, rs1_store {mask: 0x0000707f, value: 0x00002023, op: SW, args: argTypeList{arg_rs2, arg_rs1_store}}, // XNOR rd, rs1, rs2 {mask: 0xfe00707f, value: 0x40004033, op: XNOR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // XOR rd, rs1, rs2 {mask: 0xfe00707f, value: 0x00004033, op: XOR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, // XORI rd, rs1, imm12 {mask: 0x0000707f, value: 0x00004013, op: XORI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, // ZEXT.H rd, rs1 {mask: 0xfff0707f, value: 0x0800403b, op: ZEXT_H, args: argTypeList{arg_rd, arg_rs1}}, }